This invention relates generally to magnetic bubble devices and more particularly to magnetic bubble devices for performing serial arithmetic operations on binary integers and special purpose pipeline processors using the same.
Magnetic bubble technology development has primarily focused on memory applications. Magnetic bubble technology has been shown to be capable of yielding relatively compact LSI chips having large memory storage capability, at relatively low cost. In some applications, bubble technology may achieve considerable advance over semiconductor technology in chip area utilization. Since it is feasible to make bubble chips larger than semi-conductor chips, bubble technology permits a greater degree of integration to be achieved. Bubble chips generally require only one critical masking step in their fabrication process. Therefore, they are more economical to produce than semiconductor chips. Furthermore, bubble devices operate on less power than most comparable semiconductor devices.
Bubble technology may also be used for logic operations. A variety of useful logic functions has been demonstrated, using the repulsive interaction between bubbles to perform logic operations. For example, U.S. Pat. Nos. 3,731,109 to Garey, 3,743,851 to Kohara, 3,750,106 to Caron and 3,909,622 to Minnick, disclose various bubble logic devices such as AND, NAND, OR, NOR, Exclusive-OR, NOT and inversion. Although the principles of bubble logic have been demonstrated, logic design exercises have produced generally pessimistic estimates of bubble logic performance in comparison to semiconductor technology. These unfavorable comparisons have been due to the constraints under which magnetic bubble devices must operate and the lack of logic designs compatible with these constraints.
One constraint on magnetic bubble technology is the relatively slow speed of bubble propagation, currently approximately 0.5 MHz in commonly used bubble materials. In addition, since bubbles propagate serially in shift register fashion along propagation paths, the geometry problems associated with the interconnection of gates and the equalization of propagation delays may be quite significant. Although various logic schemes have been suggested to avoid some of these difficulties, bubble logic designs, for the most part, have been aimed at achieving a general purpose logic capability which is obtained at the expense of globally efficient designs. For example, U.S. Pat. No. 3,798,607 to Minnick, discloses a general purpose computer design based upon bubble technology. This computer executes instructions slowly and consequently its applications are very limited. It is clear from the intrinsic characteristics of bubble technology, that arbitrary interconnections of bubble logic gates cannot be accomplished with efficient utilization of chip area. Nevertheless, specific applications exist where the required data rate is matched to the bubble propagation speed and where pipeline bubble logic designs can be implemented efficiently in terms of chip area utilization, with minimum area devoted to gate interconnections and bubble generators and annihilators.
The inherent serial nature of magnetic bubble technology makes it ideally suited to a pipeline computational structure with a minimum of internal feedback. Assuming a 0.5 MHz bubble propagation rate, 16-bit words, and one propagation period per bit, the throughput of a pipeline processor utilizing bubble technology could be 30,000 words per second, which represents a capability of processing signals of 15 KHz bandwidth. This speed is adequate for many applications. For example, the speed required for voice processing is well within the capability of existing bubble technology.
It is desirable therefore and an object of the invention in its most general sense, to provide pipeline designs for serial arithmetic bubble devices which will take maximum advantage of the characteristics of magnetic bubble technology and which will form the basis for the designs of special purpose processors, for applications which lend themselves to pipeline processing.
Accordingly, an approach to the design of serial arithmetic devices has been developed using principles which are intended to facilitate the hardware design and to achieve maximum use of chip area. The same type of bubble interaction, i.e., bubble repulsion to prevent bubble transfer, is used in all gates so that their design will be similar. Furthermore, only two-input gates are used since these structures are the simplest and require the least development effort. Although three-input gates may be used, they are more complicated and are not essential for achieving a reasonably compact design. My designs for serial arithmetic elements demonstrate that serial arithmetic can be performed by a compact arrangement of a small number of different types of basic bubble logic gates. These basic circuits are not burdened with excessive numbers of bubble generators, annihilators, or crossovers, and no problem is encountered with fan out. Furthermore, by using only two-input gates and a pipeline computational structure, the geometry of the circuits is significantly simplified. This facilitates the hardware design and permits reasonably high computing power to chip area ratios to be achieved. Consequently, special purpose pipeline bubble logic processors utilizing these designs can be made to compare favorably with conventional semiconductor logic designs.
To facilitate an understanding of the invention, it is helpful to define certain terminology used herein. The term "element" refers to the various two-input bubble logic gates and components illustrated in FIGS. 1 and 2, and the incremental adder of FIG. 3A which form the basic building blocks for implementing circuits which perform arithmetic operations. A "unit" is an interconnection of elements which performs some function, such as an arithmetic operation. The term "device" refers generically to an interconnection of units or elements. The term "pipeline" refers to the structure of a device in which the geometry of its units is such that processing operations are sequentially performed on a continuous flow of serial data through the units, without data feedback paths internal to the units.
A magnetic bubble device for performing serial integer arithmetic on binary integers which provides the aforementioned and other advantages may include input means for two magnetic bubble streams that are representative of two binary integers upon which the arithmetic operation is to be performed, output means for outputting a magnetic bubble stream which is representative of the result of the arithmetic operation and an arithmetic unit comprising a plurality of magnetic bubble elements, including at least a first two-input bubble logic gate for performing a logical operation on two binary integers input to the gate, the elements being interconnected in a predetermined pipeline configuration between the input and output means, for performing a predetermined arithmetic operation on the binary integers.